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| 說明 | 1 online resource (114 pages) |
| 文字 | text |
| 無媒介 | computer |
| 成冊 | online resource |
| 附註 | Source: Dissertations Abstracts International, Volume: 81-11, Section: B |
| Advisor: Smith, Scott C |
| Thesis (Ph.D.)--University of Arkansas, 2020 |
| Includes bibliographical references |
| This dissertation proposes a Built-In Self-Test (BIST) hardware implementation for Multi-Threshold NULL Convention Logic (MTNCL) circuits. Two different methods are proposed: an area-optimized topology that requires minimal area overhead, and a test-performance-optimized topology that utilizes parallelism and internal hardware to reduce the overall test time through additional controllability points. Furthermore, an automated software flow is proposed to insert, simulate, and analyze an input MTNCL netlist to obtain a desired fault coverage, if possible, through iterative digital and fault simulations. The proposed automated flow is capable of producing both area-optimized and test-performance-optimized BIST circuits and scripts for digital and fault simulation using commercial software that may be utilized to manually verify or adjust further, if desired |
| Electronic reproduction. Ann Arbor, Mich. : ProQuest, 2021 |
| Mode of access: World Wide Web |
| 主題 | Electrical engineering |
| Computer engineering |
| Asynchronous logic |
| Built-in self-test (BIST) |
| Multi-threshold NULL Convention Logic (MTNCL) |
| NULL convention logic (NCL) |
| Sleep convention logic (SCL) |
| Electronic books. |
| 0544 |
| 0464 |
| ISBN/ISSN | 9798644902286 |
