MARC 主機 00000nam 2200000 4500
001 AAI3167176
005 20051128082915.5
008 051128s2005 s eng d
020 054202604X
035 (UnM)AAI3167176
040 UnM|cUnM
100 1 Zhang, Chuang
245 10 Techniques for low power analog, digital and mixed signal
CMOS integrated circuit design|h[electronic resource]
300 179 p
500 Source: Dissertation Abstracts International, Volume: 66-
03, Section: B, page: 1647
500 Director: Ashok Srivastava
502 Thesis (Ph.D.)--Louisiana State University and
Agricultural & Mechanical College, 2005
520 With the continuously expanding of market for portable
devices such as wireless communication devices, portable
computers, consumer electronics and implantable medical
devices, low power is becoming increasingly important in
integrated circuits. The low power design can increase
operation time and/or utilize a smaller size and lighter-
weight battery. In this dissertation, several low power
complementary metal-oxide-semiconductor (CMOS) integrated
circuit design techniques are investigated
520 A metal-oxide-semiconductor field effect transistor
(MOSFET) can be operated at a lower voltage by forward-
biasing the source-substrate junction. This approach has
been investigated in detail and used to designing an ultra
-low power CMOS operational amplifier for operation at +/-
0.4 V. The issue of CMOS latchup and noise has been
investigated in detail because of the forward biasing of
the substrates of MOSFETs in CMOS. With increasing forward
body-bias, the leakage current increases significantly.
Dynamic threshold MOSFET (DTMOS) technique is proposed to
overcome the drawback which is inherent in a forward-
biased MOSFET. By using the DTMOS method with the forward
source-body biased MOSFET, two low-power low-voltage CMOS
VLSI circuits that of a CMOS analog multiplexer and a
Schmitt trigger circuits are designed. In this
dissertation, an adaptive body-bias technique is proposed.
Adaptive body-bias voltage is generated for several
operational frequencies. Another issue, which the chip
design community is facing, is the development of portable,
cost effective and low power supply voltage. This
dissertation proposes a new cost-effective DC/DC converter
design in standard 1.5 mum n-well CMOS, which adopts a
delay-line controller for voltage regulation
590 School code: 0107
650 4 Engineering, Electronics and Electrical
690 0544
710 20 Louisiana State University and Agricultural & Mechanical
College
773 0 |tDissertation Abstracts International|g66-03B
856 40 |uhttps://pqdd.sinica.edu.tw/twdaoapp/servlet/
advanced?query=3167176
912 PQDT
